|R0||=||bit bucket and source of zero value|
|R1||=||target of ADDIL (Add Immediate Literal)|
|R2||=||RP Return Pointer where BL places address and where BV gets it|
|R23||=||fourth parameter of a procedure call|
|R24||=||third parameter of a procedure call|
|R25||=||second parameter of a procedure call|
|R26||=||first parameter of a procedure call|
|R27||=||DP Data Pointer to base of global data|
|R28-29||=||function result in R28 if 32-bits, both if 64-bits|
|R30||=||SP Stack Pointer to parameters and exit data|
|R31||=||receives target branch address in BLE instruction|
If a procedure has more than four parameters, the rest are passed
in the stack. The fifth is usually at [SP-$32] or [SP-$34]. On
MPE, see the
Cseq calling sequence utility.
For registers to address virtual memory, they must be combined
explicitly or implicitly with a
In addition to 32 general-purpose
computers have eight 32-bit Space Registers: SR0 to SR7.
is increased vastly when a 32-bit Space Identifier is combined with a
|SR 0||=||return address of inter-space procedure calls|
|SR 1||=||Temporary use for constructing long pointers|
|SR 2||=||Temporary use for constructing long pointers|
|SR 3||=||Temporary use for constructing long pointers|
|SR 4||=||Code space|
|SR 5||=||process private data: stack and heap|
|SR 6||=||Shared data|
|SR 7||=||System public code, literals, and data|
The machine instructions
specify a Space Register when referencing code or data in memory.
LDW 1000(0,27),10 instruction, the
Space Id is 0, the Offset is Base Register 27 plus Displacement
1000, and the Target is register 10.
Space Id 0 is a special case
where the Space Register is computed as 4 plus the first 2 bits of
the value in the Base Register.
For user data, those bits are usually 1, specifying SR5.
Since two bits of the offset have been consumed, this type
of address can only access a
not a full 4-gigabyte space.