Because CM code is emulated, it is usually much slower than NM
code. It is possible for a program to switch between CM and
NM many times during execution, especially because parts of the
MPE/iX operating system are still written in CM.
If the number of
such CM switches per second is high, it can cause
slow system performance.
Object Code Translator
If you don't have the source code for a program, or
the time to convert it to Native mode, you can still
improve the performance by running the CM program file
through the Object Code Translator
(OCT). This usually
yields a substantial performance improvement, unless
the program is totally I/O bound. OCT creates a single file
containing both the CM code and translated NM code. If you
patch the CM code in such a file, the NM code is not
updated; you need to run
Octcomp for that.
Native Mode on MPE
The instruction set of the
computers is called Native mode,
as opposed to the emulated and slower execution of
Native mode is also know as NM.
Every process has an NM Stack where it stores parameters and local
for NM procedures and a CM Stack for CM procedures. NM procedures can
call CM, and vice versa, through "Switches" that translate parameters
between the two stacks.
On the PA-RISC machines each process has a
stack and a native-mode heap. On MPE/iX, processes also have a
stack, which simulates the stack design of the Classic HP 3000
On HP-UX and MPE/iX, a
procedure call pushes a complex stack marker onto the native mode stack.
On MPE V and in
an eight-byte "return address" is pushed onto your stack
when you call a procedure; the Q register
points to the current stack marker:
|Q-3||X||Index Register value to reset on EXIT|
|Q-2||Delta P||Instruction to return to in code segment|
|Q-1||Status||Includes code segment in right byte|
|Q-0||Delta Q||Subtract Q-0 from Q to find previous Q|
Q-1 contains a copy of the Status Register,
which contains the Condition Code.
The right-most 14 bits of Q-2 are the Return Address (2:14).
Under MPE V,
the second bit of Q-2 (1:1) is 1 if
Q-2 contains a physical code segment number (0 for logical).
On MPE V and in
the status register is a
16-bit hardware register that retains program modes
and the current code segment (CST). It is saved in Q-1 on procedure call as part
of the return address.
|M||I||T||R||O||C||CC||Code Segment Number|
|T||Arithmetic Traps Enabled|
|O||Overflow on last opcode|
|I||External Interrupts Enabled|
|R||Right Stack Op Pending|
|C||Carry on last opcode|
|CC||Condition code: CCL = 1, CCE = 2, CCG = 0.|
Under MPE V there is a hidden bit (also called M) that is 1 if
the code segment number is physical, not logical
(saved as bit 1 of Q-2 in Stack Marker).
Condition Code in MPE
Condition code is a feature of the Classic HP 3000 architecture which keeps track
of the result of the last instruction and/or intrinsic.
The Condition code is fragile because it is changed by most things you
simulates the Condition code in order to maintain backward
compatibility with MPE V. However, new intrinsics such as
HPFOPEN and HPCIGETVAR do not return status through the
Condition code; only old intrinsics such as FOPEN and FREAD
which were carried forward from MPE V
On MPE V or in Compatibility Mode of MPE/iX, the Condition code resides in bits 6 and 7 of the Status Register. Two bits allows four possible values:
There are five ways to interpret the Condition Code value:
|CCL <||CCE =||CCG >|
|CCD||not respd||dev ready||dev busy|
|Intrinsic||hard error||success||softer error|